In current digital circuits the supply current varies widely depending upon the operating states of the circuit. Especially in circuits for portable devices current consumption has to be minimized during idle phases of the system. All parts of the system reduce their current consumption as long as no data processing is required to reduce the current drawn from the battery. When data processing restarts the current consumption rises sharply. By reducing the idle mode current in all parts of the system, the current step caused by the return to an active state is increased.
A similar change of supply current can occur when data processing stops. Processor cores can enter a wait-for-interrupt state and generate a signal permitting turn-off of the clock to the major part of the processor core. Only a small part containing the interrupt handling logic remains clocked. Similar functions are often provided by signal processing blocks.
In current portable systems many sources can trigger the restart of data processing in different parts of the circuit, e.g. a keypad interrupt or a signal received via network link. These events occur completely asynchronously to each other and may in rare cases trigger a simultaneous step in the current consumption in all parts of the system. This type of extreme current surge has to be handled by the voltage regulator supplying the voltage of the device.
The voltage regulator has to maintain the supply voltage within a very narrow voltage tolerance range and has to minimize under- and overshoots of the supply voltage. The minimum supply voltage is usually defined by the performance requirements of the supplied circuit, the maximum supply voltage may be defined by technological limits. Furthermore minimizing the supply voltage reduces the power consumption of the circuit.
Selecting large output capacitors and optimizing the design of the voltage regulator are standard approaches to minimize supply voltage transients presently used. Large output capacitors, however, increase the cost and the board footprint of the voltage regulator circuitry. Optimizing the voltage regulator for minimum voltage transients often requires higher quiescent currents and thereby reduced power efficiency of the voltage regulators. In most cases a significant supply voltage tolerance will be unavoidable which often requires a reduction of the minimum supply voltage. Thereby the achievable performance of the circuit is reduced.